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| a FEATURES Differential Amplification Wide Common-Mode Voltage Range: +12.8 V, -12 V Differential Voltage Range: 2 V High CMRR: 60 dB @ 4 MHz Built-in Differential Clipping Level: 2.3 V Fast Dynamic Performance 85 MHz Unity Gain Bandwidth 35 ns Settling Time to 0.1% 360 V/ s Slew Rate Symmetrical Dynamic Response Excellent Video Specifications Differential Gain Error: 0.06% Differential Phase Error: 0.08 15 MHz (0.1 dB) Bandwidth Flexible Operation High Output Drive of 50 mA min Specified with Both 5 V and 15 V Supplies Low Distortion: THD = -72 dB @ 4 MHz Excellent DC Performance: 3 mV max Input Offset Voltage APPLICATIONS Differential Line Receiver High Speed Level Shifter High Speed In-Amp Differential to Single Ended Conversion Resistorless Summation and Subtraction High Speed A/D Driver PRODUCT DESCRIPTION -50 RL = 150 GAIN = +1 -60 High Speed, Video Difference Amplifier AD830 CONNECTION DIAGRAM 8-Pin Plastic Mini-DIP (N), Cerdip (Q) and SOIC (R) Packages VOUT = 2V p-p HARMONIC DISTORTION - dBc 5V SUPPLIES 2ND HARMONIC 3RD HARMONIC -70 -80 15V SUPPLIES 2ND HARMONIC 3RD HARMONIC -90 1k 10k 100k FREQUENCY - Hz 1M 10M input and produces an output voltage referred to a user-chosen level. The undesired common-mode signal is rejected, even at high frequencies. High impedance inputs ease interfacing to finite source impedances and thus preserve the excellent common-mode rejection. In many respects, it offers significant improvements over discrete difference amplifier approaches, in particular in high frequency common-mode rejection. The wide common-mode and differential-voltage range of the AD830 make it particularly useful and flexible in level shifting applications, but at lower power dissipation than discrete solutions. Low distortion is preserved over the many possible differential and common-mode voltages at the input and output. Good gain flatness and excellent differential gain of 0.06% and phase of 0.08 make the AD830 suitable for many video system applications. Furthermore, the AD830 is suited for general purpose signal processing from dc to 10 MHz. 9 6 3 VS = 5V RL = 150 CL = 33pF The AD830 is a wideband, differencing amplifier designed for use at video frequencies but also useful in many other applications. It accurately amplifies a fully differential signal at the 110 100 90 0 CMRR - dB 80 70 60 50 GAIN - dB VS = 15V -3 -6 -9 -12 CL = 15pF -15 CL = 4.7pF VS = 5V 40 30 1k 10k 100k FREQUENCY - Hz 1M 10M -18 -21 10k 100k 1M 10M 100M 1G FREQUENCY - Hz Common-Mode Rejection Ratio vs. Frequency Closed-Loop Gain vs. Frequency, Gain = +1 REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD830-SPECIFICATIONS Parameter DYNAMIC CHARACTERISTICS 3 dB Small Signal Bandwidth 0.1 dB Gain Flatness Frequency Differential Gain Error Differential Phase Error Slew Rate 3 dB Large Signal Bandwidth Settling Time, Gain = 1 Harmonic Distortion Input Voltage Noise Input Current Noise DC PERFORMANCE Offset Voltage Open Loop Gain Gain Error Peak Nonlinearity, R L= 1 k, Gain = 1 Input Bias Current Input Offset Current INPUT CHARACTERISTICS Differential Voltage Range Differential Clipping Level 2 Common-Mode Voltage Range CMRR (VS = 15 V, RLOAD = 150 , CLOAD = 5 pF, TA = +25 C unless otherwise noted) AD830J/A AD830S1 Conditions Gain = 1, VOUT = 100 mV rms Gain = 1, VOUT = 100 mV rms 0 to +0.7 V, Frequency = 4.5 MHz 0 to +0.7 V, Frequency = 4.5 MHz 2 V Step, RL = 500 4 V Step, RL = 500 Gain = 1, VOUT = 1 V rms VOUT = 2 V Step, to 0.1% VOUT = 4 V Step, to 0.1% 2 V p-p, Frequency = 1 MHz 2 V p-p, Frequency = 4 MHz Frequency = 10 kHz Min 75 11 Typ 85 15 0.06 0.08 360 350 45 25 35 -82 -72 27 1.4 1.5 Max Min 75 11 Typ 85 15 0.06 0.08 360 350 45 25 35 -82 -72 27 1.4 1.5 Max Units MHz MHz % Degrees V/s V/s MHz ns ns dBc dBc nV/Hz pA/Hz mV mV dB % % FS % FS % FS A A A V V V dB dB dB k pF V V mA mA V mA dB dB dB dB 0.09 0.12 0.09 0.12 38 38 Gain = 1 Gain = 1, TMIN-TMAX DC RL = 1 k, G = 1 -1 V X +1 V -1.5 V X +1.5 V -2 V X +2 V VIN = 0 V, +25C to TMAX VIN = 0 V, TMIN VIN = 0 V, TMIN-TMAX VCM = 0 Pins 1 and 2 Inputs Only VDM = 1 V DC, Pins 1, 2, 10 V DC, Pins 1, 2, 10 V, TMIN-TMAX Frequency = 4 MHz 3 5 0.6 0.03 0.07 0.4 10 13 1 64 3 7 0.6 0.03 0.07 0.4 10 17 1 64 69 0.1 0.01 0.035 0.15 5 7 0.1 2.0 2.3 69 0.1 0.01 0.035 0.15 5 8 0.1 2.0 2.3 2.1 -12.0 90 88 55 +12.8 100 60 370 2 +13.8, -13.8 +15.3, -14.7 80 2.1 -12.0 90 86 55 +12.8 100 60 370 2 +13.8, -13.8 +15.3, -14.7 80 Input Resistance Input Capacitance OUTPUT CHARACTERISTICS Output Voltage Swing Short Circuit Current Output Current POWER SUPPLIES Operating Range Quiescent Current + PSRR (to VP) - PSRR (to VN) PSRR PSRR RL 1 k RL 1 k, 16.5 VS Short to Ground RL = 150 12 13 50 4 TMIN-TMAX DC, G = 1 DC, G = 1 DC, G = 1, 5 to 15 VS DC, G = 1, 5 to 15 VS, TMIN-TMAX 12 13 50 4 66 62 14.5 86 68 71 68 16.5 17 66 60 14.5 86 68 71 68 16.5 17 NOTES 1 See Standard Military Drawing 5962-9313001MPA for specifications. 2 Clipping level function on X channel only. Specifications subject to change without notice. -2- REV. A AD830 (VS = 5 V, RLOAD = 150 , CLOAD = 5 pF, TA = +25 C unless otherwise noted) Conditions Min 35 5 AD830J/A Typ Max 40 6.5 0.14 0.32 210 240 36 35 48 -69 -56 27 1.4 1.5 60 65 0.1 0.01 0.045 0.23 5 7 0.1 2.0 2.2 +2.9 100 0.18 0.4 Min 35 5 AD830S1 Typ Max 40 6.5 0.14 0.32 210 240 36 35 48 -69 -56 27 1.4 1.5 60 65 0.1 0.01 0.045 0.23 5 8 0.1 2.0 2.2 +2.9 100 0.18 0.4 Units MHz MHz % Degrees V/s V/s MHz ns ns dBc dBc nV/Hz pA/Hz mV mV dB % % FS % FS % FS A A A V V V dB dB dB k pF V V mA mA 16.5 16 V mA dB dB dB dB Parameter DYNAMIC CHARACTERISTICS 3 dB Small Signal Bandwidth Gain = 1, VOUT = 100 mV rms 0.1 dB Gain Flatness Frequency Gain = 1, VOUT = 100 mV rms Differential Gain Error 0 to +0.7 V, Frequency = 4.5 MHz, G = +2 Differential Phase Error 0 to +0.7 V, Frequency = 4.5 MHz, G = +2 Slew Rate, Gain = 1 2 V Step, RL = 500 4 V Step, RL = 500 3 dB Large Signal Bandwidth Gain = 1, VOUT = 1 V rms Settling Time VOUT = 2 V Step, to 0.1% VOUT = 4 V Step, to 0.1% Harmonic Distortion 2 V p-p, Frequency = 1 MHz 2 V p-p, Frequency = 4 MHz Input Voltage Noise Frequency = 10 kHz Input Current Noise DC PERFORMANCE Offset Voltage Open Loop Gain Unity Gain Accuracy Peak Nonlinearity, RL= 1 k Gain = 1 Gain = 1, TMIN-TMAX DC RL = 1 k -1 V X +1 V -1.5 V X +1.5 V -2 V X +2 V VIN = 0 V, +25C to TMAX VIN = 0 V, TMIN VIN = 0 V, TMIN-TMAX VCM = 0 Pins 1 and 2 Inputs Only VDM = 1 V DC, Pins 1, 2, +4 V to -2 V DC, Pins 1, 2, +4 V to -2 V, TMIN-TMAX Frequency = 4 MHz 30 30 3 4 0.6 0.03 0.07 0.4 10 13 1 3 5 0.6 0.03 0.07 0.4 10 17 1 Input Bias Current Input Offset Current INPUT CHARACTERISTICS Differential Voltage Range Differential Clipping Level 2 Common-Mode Voltage Range CMRR 2.0 -2.0 90 88 55 2.0 -2.0 90 86 55 Input Resistance Input Capacitance OUTPUT CHARACTERISTICS Output Voltage Swing Short Circuit Current Output Current POWER SUPPLIES Operating Range Quiescent Current + PSRR (to VP) - PSRR (to VN) PSRR (Dual Supply) PSRR (Dual Supply) RL 150 RL 150 , 4 VS Short to Ground 3.2 2.2 40 4 TMIN-TMAX DC, G = 1, Offset DC, G = 1, Offset DC, G = 1, 5 to 15 VS DC, G = 1, 5 to 15 VS, TMIN-TMAX 60 370 2 3.5 +2.7, -2.4 -55, +70 60 370 2 3.5 +2.7, -2.4 -55, +70 3.2 2.2 40 16.5 16 4 66 62 13.5 86 68 71 68 66 60 13.5 86 68 71 68 NOTES 1 See Standard Military Drawing 5962-9313001MPA for specifications. 2 Clipping level function on X channel only. Specifications subject to change without notice. REV. A -3- AD830 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation2 . . . . . . . Observe Derating Curves Output Short Circuit Duration . . . . Observe Derating Curves Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VS Storage Temperature Range (Q) . . . . . . . . . -65C to +150C Storage Temperature Range (N) . . . . . . . . . -65C to +125C Storage Temperature Range (R) . . . . . . . . . -65C to +125C Operating Temperature Range AD830J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C AD830A . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C AD830S . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Lead Temperature Range (Soldering 60 seconds) . . . +300C NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-Pin Plastic Package: JA = 90C/Watt 8-Pin SOIC Package: JA = 155C/Watt 8-Pin Cerdip Package: JA = 110C/Watt ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD830 is limited by the associated rise in junction temperature. For the plastic packages, the maximum safe junction temperature is 145C. For the cerdip, the maximum junction temperature is 175C. If these maximums are exceeded momentarily, proper circuit operation will be restored as soon as the die temperature is reduced. Leaving the AD830 in the "overheated" condition for an extended period can result in permanent damage to the device. To ensure proper operation, it is important to observe the recommended derating curves. While the AD830 output is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. If the output is shorted to a supply rail for an extended period, then the amplifier may be permanently destroyed. ESD SUSCEPTIBILITY ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without detection. Although the AD830 features proprietary ESD protection circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. ORDERING GUIDE Model AD830AN AD830JR 5962-9313001MPA* Temperature Range -40C to +85C 0C to +70C -55C to +125C Package Description 8-Pin Plastic Mini-DIP 8-Pin SOIC 8-Pin Cerdip Package Option N-8 R-8 Q-8 *See Standard Military Drawing for specifications. 2.5 3.0 TJ MAX = 145C TOTAL POWER DISSIPATION - Watts 2.8 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 8-PIN CERDIP TOTAL POWER DISSIPATION - Watts TJ MAX = 175C 2.0 8-PIN MINI-DIP 1.5 1.0 0.5 8-PIN SOIC 0 -50 -30 -10 10 30 50 AMBIENT TEMPERATURE - C 70 90 0.2 -60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE - C 120 140 Maximum Power Dissipation vs. Temperature, Mini-DlP and SOIC Packages Maximum Power Dissipation vs. Temperature, Cerdip Package -4- REV. A Typical Characteristics- AD830 110 100 90 80 70 60 50 40 30 1k 10k 100k FREQUENCY - Hz 1M 10M VS = 15V 100 90 80 70 TO V P @ 15V TO VP @ 5V TO VN @ 15V CMRR - dB PSRR - dB 60 TO VN @ 5V 50 40 30 20 10 1k 10k 100k FREQUENCY - Hz 1M 10M VS = 5V Figure 1. Common-Mode Rejection Ratio vs. Frequency Figure 4. Power Supply Rejection Ratio vs. Frequency -50 VOUT = 2V p-p HARMONIC DISTORTION - dBc 3 RL = 150 GAIN = +1 0 15V -3 5V SUPPLIES 2ND HARMONIC 3RD HARMONIC GAIN - dB -6 -9 -12 -15 -18 -21 -24 5V RL = 150 CL = 4.7pF 10V -60 -70 -80 15V SUPPLIES 2ND HARMONIC 3RD HARMONIC -90 1k 10k 100k FREQUENCY - Hz 1M 10M -27 10k 100k 1M 10M 100M 1G FREQUENCY - Hz Figure 2. Harmonic Distortion vs. Frequency Figure 5. Closed-Loop Gain vs. Frequency G = +1 9 3 5V S 8 INPUT OFFSET VOLTAGE - mV INPUT CURRENT - A 2 1 7 10V S 0 -1 15V S 6 5 -2 4 -3 3 -60 -40 -20 0 20 40 60 80 100 120 140 -4 -60 -40 -20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE - C JUNCTION TEMPERATURE - C Figure 3. Input Bias Current vs. Temperature Figure 6. Input Offset Voltage vs. Temperature REV. A -5- AD830 0.10 0.09 DIFFERENTIAL GAIN - % 0.10 GAIN = +2 RL = 500 FREQ = 4.5MHz 0.09 DIFFERENTIAL GAIN - % 0.08 0.07 PHASE 0.06 0.05 0.04 0.03 0.02 GAIN 0.01 13 14 15 DIFFERENTIAL PHASE - Degrees 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 5 6 7 PHASE GAIN GAIN = +2 RL = 150 FREQ = 4.5MHz 0.40 0.36 0.32 0.28 0.24 0.20 0.16 0.12 0.08 0.04 13 14 15 DIFFERENTIAL PHASE - Degrees 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE - Volts 8 9 10 11 12 SUPPLY VOLTAGE - Volts Figure 7. Differential Gain and Phase vs. Supply Voltage, RL = 500 Figure 10. Differential Gain and Phase vs. Supply Voltage, RL = 150 -40 -40 -50 HARMONIC DISTORTION - dB HARMONIC DISTORTION - dB -50 HD2 (5V) 4MHz -60 -60 HD3 (5V) 4MHz HD2 (15V) 4MHz -70 HD3 (5V) 100kHz HD3 (15V) 100kHz -70 -80 -80 -90 HD2 (5V) 100kHz -100 0.25 0.50 0.75 1.00 1.25 1.50 HD2 (15V) 100kHz 1.75 2.00 -90 HD3 (15V) 4MHz 0.50 0.75 1.00 1.25 1.50 1.75 2.00 -100 0.25 PEAK AMPLITUDE - Volts PEAK AMPLITUDE - Volts Figure 8. Harmonic Distortion vs. Peak Amplitude, Frequency = 100 kHz Figure 11. Harmonic Distortion vs. Peak Amplitude, Frequency = 4 MHz 50 15.00 14.75 QUIESCENT SUPPLY CURRENT- mA INPUT VOLTAGE NOISE - nV/Hz 14.50 14.25 14.00 13.75 13.50 13.25 13.00 12.75 12.50 16.5V S 40 30 5V S 20 10 100 1k 10k 100k 1M 10M 12.25 -60 -40 -20 0 20 40 60 80 100 120 140 FREQUENCY - Hz JUNCTION TEMPERATURE - C Figure 9. Noise Spectral Density Figure 12. Supply Current vs. Junction Temperature -6- REV. A Typical Characteristics- AD830 3 0 15V -3 UNITY GAIN CONNECTION -6 -9 -12 -15 -18 -21 -24 -27 100k 5V RL = 150 CL = 0pF 3 GAIN OF 2 CONNECTION 3 4 9 V1 6 1 2 GM AD830 A=1 8 7 6 5 VP OUT 0 -3 -6 -9 -12 -15 GM C VN VOUT = 2V1 RESISTOR LESS GAIN OF 2 (a) 1 2 GM AD830 A=1 8 7 6 VP OUT -18 V1 -21 1M 10M FREQUENCY - Hz 100M 1G 3 4 GM C 5 VN Figure 13. Closed-Loop Gain vs. Frequency for the Three Common Connections of Figure 16 V1 1 2 VOUT = V 1 OP-AMP CONNECTION (b) GM AD830 A=1 8 7 6 5 VP OUT 100 90 100mV VS = 5V 3 4 GM C VN VOUT = V 1 GAIN OF 1 (c) Figure 16. Connection Diagrams VS = 15V 10 0% 100 1V VS = 5V 20ns 90 Figure 14. Small Signal Pulse Response, RL = 150 , CL = 4.7 pF, G = +1 10 0% VS = 15V 9 6 3 0 GAIN - dB -3 -6 -9 -12 -15 -18 -21 10k CL = 4.7pF CL = 15pF VS = 5V RL = 150 CL = 33pF 20ns Figure 17. Large Signal Pulse Response, RL = 150 , CL = 4.7 pF, G = +1 9 6 3 0 VS = +15V RL = 150 CL = 33pF CL = 15pF GAIN - dB -3 -6 -9 -12 -15 -18 -21 10k CL = 4.7pF 100k 1M 10M 100M 1G FREQUENCY - Hz Figure 15. Closed-Loop Gain vs. Frequency vs. CL, G = +1. VS = 5 V 100k 1M 10M 100M 1G FREQUENCY - Hz Figure 18. Closed-Loop Gain vs. Frequency, vs. CL, G = +1. VS = 15 V REV. A -7- AD830 TRADITIONAL DIFFERENTIAL AMPLIFICATION AD830 FOR DIFFERENTIAL AMPLIFICATION In the past, when differential amplification was needed to reject common-mode signals superimposed with a desired signal; most often the solution used was the classic op amp based difference amplifier shown in Figure 19. The basic function VO = V1-V2 is simply achieved, but the overall performance is poor and the circuit possesses many serious problems that make it difficult to realize a robust design with moderate to high levels of performance. R1 V2 R2 The AD830 amplifier was specifically developed to solve the listed problems with the discrete difference amplifier approach. Its topology, discussed in detail in a later section, by design acts as a difference amplifier. The circuit of Figure 20 shows how simply the AD830 is configured to produce the difference of two signals V1 and V2, in which the applied differential signal is exactly reproduced at the output relative to a separate output common. Any common-mode voltage present at the input is removed by the AD830. V1 V I R3 V1 R4 V2 VOUT IX A=1 IY V I VOUT = V 1 - V 2 VOUT ONLY IF R 1 = R 2 = R 3 = R 4 DOES VOUT = V 1 - V 2 Figure 19. Op Amp Based Difference Amplifier PROBLEMS WITH THE OP AMP BASED APPROACH * Low Common-Mode Rejection Ratio (CMRR) * Low Impedance Inputs * CMRR Highly Sensitive to the Value of Source R * Different Input Impedance for the + and - Input * Poor High Frequency CMRR * Requires Very Highly Matched Resistors R1-R4 to Achieve High CMRR * Halves the Bandwidth of the Op Amp * High Power Dissipation in the Resistors for Large CommonMode Voltage Figure 20. AD830 as a Difference Amplifier ADVANTAGEOUS PROPERTIES OF THE AD830 * High Common-Mode Rejection Ratio (CMRR) * High Impedance Inputs * Symmetrical Dynamic Response for +1 and -1 Gain * Low Sensitivity to the Value of Source R * Equal Input Impedance for the + and - Input * Excellent High Frequency CMRR * No Halving of the Bandwidth * Constant Power Distortion vs. Common-Mode Voltage * Highly Matched Resistors Not Needed -8- REV. A AD830 UNDERSTANDING THE AD830 TOPOLOGY The AD830 represents Analog Devices' first amplifier product to embody a powerful alternative amplifier topology. Referred to as active feedback, the topology used in the AD830 provides inherent advantages in the handling of differential signals, differing system commons, level shifting and low distortion, high frequency amplification. In addition, it makes possible the implementation of many functions not realizable with single op amp circuits or is superior to op amp based equivalent circuits. With this in mind, it is important to understand the internal structure of the AD830. The topology, reduced to its elemental form, is shown below in Figure 21. Nonideal effects such as nonlinearity, bias currents and limited full scale are omitted from this model for simplicity, but are discussed later. The key feature of this topology is the use of two, identical voltage-to-current converters, GM, that make up input and feedback signal interfaces. They are labeled with inputs VX and VY, respectively. These voltage to current converters possess fully differential inputs, high linearity, high input impedance and wide voltage range operation. This enables the part to handle large amplitude differential signals; they also provide high common-mode rejection, low distortion and negligible loading on the source. The label, GM, is meant to convey that the transconductance is a large signal quantity, unlike in the front-end of most op amps. The two GM stage current outputs IX and IY, sum together at a high impedance node which is characterized by an equivalent resistance and capacitance connected to an "ac common." A unity voltage gain stage follows the high impedance node to provide buffering from loads. Relative to either input, the open loop gain, AOL, is set by the transconductance, GM, working into the resistance, RP; AOL = GM RP. The unity gain frequency 0 dB for the open loop gain is established by the transconductance, GM, working into the capacitance, CC; 0 dB = GM/CC. The open loop description of the AD830 is shown below for completeness. VX1 VX2 GM IX IZ A=1 IY VY1 GM VY2 CC RP VOUT VX1 VX2 GM IX A=1 IY VY1 GM VY2 VX1 - V X2 = V Y2 - V Y1 FOR V Y2 = V OUT VOUT = (V X1 - V X2 + V Y1 ) 1 1 + S(C C /G M) CC VOUT Figure 22. Closed-Loop Connection Precise amplification is accomplished through closed-loop operation of this topology. Voltage feedback is implemented via the Y GM stage in which where the output is connected to the -Y input for negative feedback as shown in Figure 22. An input signal is applied across the X GM stage, either fully differentially or single-ended referred to common. It produces a current signal which is summed at the high impedance node with the output current from the Y GM stage. Negative feedback nulls this sum to a small error current necessary to develop the output voltage at the high impedance node. The error current is usually negligible, so the null condition essentially forces the Y GM output stage current to exactly equal the X GM output current. Since the two transconductances are identical, the differential voltage across the Y inputs equals the negative of the differential voltage across the X input; VY = -VX or more precisely VY2-VY1 = VX1-VX2. This simple relation provides the basis to easily analyze any function possible to synthesize with the AD830, including any feedback situation. The bandwidth of the circuit is defined by the GM and the capacitor CC. The highly linear GM stages give the amplifier a single pole response, excluding the output amplifier and loading effects. It is important to note that the bandwidth and general dynamic behavior is symmetrical (identical) for the noninverting and the inverting connections of the AD830. In addition, the input impedance and CMRR are the same for either connections. This is very advantageous and unlike in a voltage or current feedback amplifier, where there is a distinct difference in performance between the inverting and noninverting gain. The practical importance of this cannot be overemphasized and is a key feature offered by the AD830 amplifier topology. IX = (V X1 - VX2 ) G M IY = (V Y1 - VY2 ) G M IZ = I X + I Y GM RP 1 + S (C C RP) AOLS = Figure 21. Topology Diagram REV. A -9- AD830 INTERFACING THE INPUT Common-Mode Voltage Range Differential Voltage Range The common-mode range of the AD830 is defined by the amplitude of the differential input signal and the supply voltage. The general definition of common-mode voltage, VCM, is usually applied to a symmetrical differential signal centered about a particular voltage as illustrated by the diagram in Figure 23. This is the meaning implied here for common-mode voltage. The internal circuitry establishes the maximum allowable voltage on the input or feedback pins for a given supply voltage. This constraint and the differential input voltage sets the common-mode voltage limit. Figure 24 shows a curve of the common-mode voltage range vs. differential voltage for three supply voltage settings. VMAX The maximum applied differential voltage is limited by the clipping range of the input stages. This is nominally set at 2.4 volts magnitude and depicted in the crossplot (X-Y) photo of Figure 25. The useful linear range of the input stages is set at 2 volts, but is actually a function of the distortion required for a particular application. The distortion increases for larger differential input voltages. A plot of relative distortion versus input differential voltage is shown in Figures 8 and 11 in the Typical Characteristics section. The distortion characteristics could impose a secondary limit to the differential input voltage for high accuracy applications. 1V 100 90 1V VCM VPEAK Figure 23. Common-Mode Definition 10 15 0% +VCM 15V = VS COMMON-MODE VOLTAGE - Volts 12 -VCM 9 10V = VS +V CM Figure 25. Clipping Behavior 15 6 -VCM +V CM MAXIMUM OUTPUT SWING - Volts VP 12 3 5V = V S 9 VN -VCM 0 0 0.4 0.8 1.2 1.6 DIFFERENTIAL INPUT VOLTAGE - V PEAK 2.0 6 Figure 24. Input Common-Mode Voltage Range vs. Differential Input Voltage 3 0 0 4 8 12 SUPPLY VOLTAGE - Volts 16 20 Figure 26. Maximum Output Swing vs. Supply -10- REV. A AD830 Choice of Polarity The sign of the gain is easily selected by choosing the polarity of the connections to the + and - inputs of the X GM stage. Swapping between inverting and noninverting gain is possible simply by reversing the input connections. The response of the amplifier is identical in either connection, except for the sign change. The bandwidth, high impedance, transient behavior, etc., of the AD830, is symmetrical for both polarities of gain. This is very advantageous and unlike an op amp. Input Impedance the peak output differential voltage can be easily derived from the maximum output swing as VOCM = VMAX-VPEAK. Output Current The relatively high input impedance of the AD830, for a differential receiver amplifier, permits connections to modest impedance sources without much loading or loss of common-mode rejection. The nominal input resistance is 300 k. The real limit to the upper value of the source resistance is in its effect on common-mode rejection and bandwidth. If the source resistance is in only one input, then the low frequency common-mode rejection will be lowered to RIN/RS. The source resistance/input 1 capacitance pole f = 2 x RS x CIN limits the bandwidth. Furthermore, the high frequency common-mode rejection will be additionally lowered by the difference in the frequency response caused by the RS CIN pole. Therefore, to maintain good low and high frequency common-mode rejection, it is recommended that the source resistances of the + and - inputs be matched and of modest value (10 k). The absolute peak output current is set by the short circuit current limiting, typically greater that 60 mA. The maximum drive capability is rated at 50 mA, but without a guarantee of distortion performance. Best distortion performance is obtained by keeping the output current 20 mA. Attempting to drive large voltages into low valued resistances (e.g., 10 V into 150 ) will cause an apparent lowering of the limit for output signal swing, but is just the current limiting behavior. Driving Cap Loads The AD830 is capable of driving modest sized capacitive loads while maintaining its rated performance. Several curves of bandwidth versus capacitive load are given in Figures 15 and 18. The AD830 was designed primarily as a low distortion video speed amplifier, but with a tradeoff, giving up very large capacitive load driving capability. If very large capacitive loads must be driven, then the network shown in Figure 27 should be used to insure stable operation. If the loss of gain caused by the resistor RS in series with the load is objectionable, then the optional feedback network shown may be added to restore the lost gain. +V S 1 VCM + INPUT SIGNAL - GM AD830 8 0.1F RS 36.5 VOUT The bias currents are typically 4 A flowing into each pin of the GM stages of the AD830. Since all applications possess some finite source resistance, the bias current through this resistor will create a voltage drop (IBIAS RS). The relatively high input impedance of the AD830 permits modest values of RS, typically 10 k. If the source resistance is in only one terminal, then an objectional offset voltage may result (e.g., 4 A 5 k = 20 mV). Placement of an equal value resistor in series with the other input will cancel the offset to first order. However, due to mismatches in the resistances, a residual offset will remain and likely be greater than bias current (offset current) mismatches. Applying Feedback Handling Bias Currents 2 ZCM A=1 7 C1 100pF R1 1k 3 C GM 6 * OPTIONAL FEEDBACK NETWORK 0.1F -V S RS 4 5 CLOSED-LOOP AMPLITUDE RESPONSE - dB The AD830 is intended for use with gain from 1 to 100. Gains greater than one are simply set by a pair of resistors connected as shown in the difference amplifier (Figure 35) with gain >1. The value of the bottom resistor R2, should be kept less than 1 k to insure that the pole formed by CIN and the parallel connection of R1 and R2 is sufficiently high in frequency so that it does not introduce excessive phase shift around the loop and destabilizes the amplifier. A compensating resistor, equal to the parallel combination of R1 and R2, should be placed in series with the other Y GM stage input to preserve the high frequency common-mode rejection and to lower the offset voltage induced by the input bias current. Output Common Mode R1 Figure 27. Circuit for Driving Large Capacitive Loads 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 10k 5V 15V The output swing of the AD830 is defined by the differential input voltage, the gain and the output common. Depending on the anticipated signal span, the output common (or ground) may be set anywhere between the allowable peak output voltage in a manner similar to that described for input voltage common mode. A plot of the peak output voltage versus supply is shown in Figure 26. A prediction of the common-mode range versus 100k 1M FREQUENCY - Hz 10M 100M Figure 28. Closed-Loop Response vs. Frequency with 100 pF Load and Series Resistor Compensation REV. A -11- AD830 SUPPLIES, BYPASSING AND GROUNDING (FIGURE 29) VP The AD830 is capable of operating over a wide range of supply voltages, both single and dual supplies. The coupling may be dc or ac provided the input and output voltages stay within the specified common-mode voltage limits. For dual supplies, the device works from 4 V to 16.5 V. Single supply operation is possible over +8 V to +33 V. It is also possible to operate the part with split supply voltages (e.g., +24 V, -5 V) for special applications such as level shifting. The primary constraint is that the total potential between the two supplies does not exceed 33 V. Inclusion of power supply bypassing capacitors is necessary to achieve stable behavior and the specified performance. It is especially important when driving low resistance loads. At a minimum, connect a 0.1 F ceramic capacitor at the supply lead of the AD830 package. In addition, for the best by passing, we recommend connecting a 0.01 F ceramic capacitor and 4.7 F tantalum capacitor to the supply lead going to the AD830. VP AND VN VP AND VN LOAD GND LEAD + VIN - 1 GM AD830 8 VOUT 2 + VICM - A=1 7 3 GM C 6 4 5 + VOUT = (V IN - V ICM ) + V OCM - VOCM Figure 30. General Single Supply Connection 30 COMMON MODE VOLTAGE LIMITS - Volts 28 24 20 16 12 8 TO GND 4 VP = +15V VP = +30V 0.1F 0.01F 4.7F LOAD GND LEAD VP = +10V (a) (b) Figure 29. Supply Decoupling Options MAXIMUM OUTPUT SWING - Volts The AD830 is designed by its functionality to be capable of rejecting noise and dissimilar potentials in the ground lines. Therefore, proper care is necessary to realize the benefits of the differential amplification of the part. Separation of the input and output grounds is crucial in rejection of the common mode noise at the inputs and eliminating any ground drops on the input signal line. For example, connecting the ground of a coaxial cable to the AD830 output common (board ground) could degrade the CMR and also introduce power-down loading on cable grounds. However, it is also necessary as in any electronic system, to provide a return path for bias currents back to their original power supply. This is accomplished by providing a connection between the differing grounds through a modest impedance labeled ZCM (e.g., 100 ). Single Supply Operation 0 0 0.4 0.8 1.2 1.6 DIFFERENTIAL INPUT VOLTAGE - V PEAK 2.0 Figure 31. Input Common-Mode Range for Single Supply 28 24 20 16 12 8 TO GND 4 TO V P The AD830 is capable of operating in single power supply applications down to a voltage of +8 V, with the generalized connection shown in Figure 30. There is a constraint on the common-mode voltage at the input and output which establishes the range for these voltages. Direct coupling may be used for input and output voltages which lie in these ranges. Any gain network applied needs to be referred to the output common connection or have an appropriate offset voltage. In situations where the signal lies at a common voltage outside the common mode range of the AD830 direct coupling will not work, so ac coupling should be used. A tested application included later in this data sheet (Figure 42), shows how to easily accomplish coupling to the AD830. For single supply operation where direct coupling is desired the input and output common-mode curves (Figures 31 and 32) should be used. -12- 0 10 14 18 22 SUPPLY VOLTAGE - Volts 26 30 Figure 32. Output Swing Limit for Single Supply REV. A AD830 Differential Line Receiver Difference Amplifier with Gain > 1 The AD830 was specifically designed to perform as a differential line receiver. The circuit in Figure 33 shows how simple it is to configure the AD830 for this function. The signal from system "A" is received differentially relative to A's common, and that voltage is exactly reproduced relative to the common in system B. The common-mode rejection versus frequency, shown in Figure 1, is excellent, typically 100 dB at low frequencies. The high input impedance permits the AD830 to operate as a bridging amplifier across low impedance terminations with negligible loading. The differential gain and phase specifications are very good as shown in Figure 7 for 500 and Figure 10 for 150 . The input and output common should be separated to achieve the full CMR performance of the AD830 as a differential amplifier. However, a common return path is necessary between systems A and B. VP V1 INPUT SIGNAL V2 COMMON IN SYSTEM A The AD830 can provide instrumentation amplifier style differential amplification at gains greater than 1. The input signal is connected differentially and the gain is set via feedback resistors as shown in Figure 35. The gain, G = (R2 + R1)/R2. The AD830 can provide either inverting or noninverting differential amplification. The polarity of the gain is established by the polarity of the connection at the input. Feedback resistors R2 should generally be R2 1 k to maintain closed-loop stability and also keep bias current induced offsets low. Highest CMRR and lowest dc offsets are preserved by including a compensating resistor in series with Pin 3. The gain may be as high as 100. VP V1 INPUT SIGNAL V2 ZCM VCM 0.1F 1 AD830 GM 0.1F 8 VOUT VCM 1 AD830 GM 8 VOUT 2 A=1 7 R1 R2 2 A=1 7 3 GM C 6 0.1F ZCM 4 3 GM C 5 R1 VN R2 6 0.1F 4 5 VN VOUT = (V1 - V2) (1+R1 /R2) VOUT = V1 - V2 COMMON IN SYSTEM B Figure 35. Gain of G Differential Amplifier, G > 1 Offsetting the Output with Gain Figure 33. Differential Line Receiver Wide Range Level Shifter The wide common-mode range and accuracy of the AD830 allows easy level shifting of differential signals referred to an input common-mode voltage to any new voltage defined at the output. The inputs may be referenced to levels as high as 10 V at the inputs with a 2 V swing about 10 V. In the circuit of Figure 34, the output voltage, VOUT, is defined by the simple equation shown below. The excellent linearity and low distortion are preserved over the full input and output common-mode range. The voltage sources need not be of low impedance, since the high input resistance and modest input bias current of the AD830 V-to-I converters permit the use of resistive voltage dividers as reference voltages. VP V1 INPUT SIGNAL V2 INPUT COMMON Some applications, such as A/D drivers, require that the signal be amplified and also offset, typically to accommodate the input range of the device. The AD830 can offset the output signal very simply through Pin 3 even with gain > 1. The voltage applied to Pin 3 must be attenuated by an appropriate factor so that V3 G = desired offset. In Figure 36, a resistive divider from a voltage reference is used to produce the attenuated offset voltage. VP V1 INPUT SIGNAL V2 ZCM R1 R2 VCM 1 AD830 GM 0.1F 8 VOUT 2 A=1 7 1 AD830 GM 0.1F 8 VOUT 3 GM C 6 0.1F 4 5 VN R1 VREF 2 A=1 7 3 GM C 6 0.1F R2 R3 VOUT = (V1 - V2) (1+R1 /R2) V3 R4 4 5 VN VOUT = V1 - V2 + V3 OUTPUT COMMON V3 Figure 36. Offsetting the Output with Differential Gain > 1 Figure 34. Differential Amplification with Level Shifting REV. A -13- AD830 Loop Through or Line Bridging Amplifier (Figure 37) The AD830 is ideally suited for use as a video line bridging amplifier. The video signal is tapped from the conductor of the cable relative to its shield. The high input impedance of the AD830 provides negligible loading on the cable. More significantly, the benign loading is maintained while the AD830 is powered-down. Coupled with its good video load driving performance, the AD830 is well suited to video cable monitoring applications. VP inputs VX1 and VY1 together and applying the input, VIN, to this wired connection. The output is exactly twice the applied voltage, VIN; VOUT = 2 VIN. Figure 39 below shows the connections for this highly useful application. The most notable characteristic of this alternative gain of two is that there is no loss of bandwidth as in a voltage feedback op amp based gain of +2 where the bandwidth is halved, therefore, the gain bandwidth is doubled. Also, this circuit is accurate without the need for any precise valued resistors, as in the op amp equivalents, and it possess excellent differential gain and phase performance as shown in Figures 40 and 41. VP 1 AD830 GM 0.1F 8 1 7 A=1 VOUT 75 AD830 GM 0.1F 8 VOUT 75 RG 249 2 VIN 2 A=1 7 3 GM 6 C 0.1F 75 3 GM 6 C 0.1F 75 4 5 499 VN OPTIONAL CC 499 4 5 VN Figure 39. Full Bandwidth Line Driver (G = +2) Figure 37. Cable Tap Amplifier Resistorless Summing .10 .09 GAIN = +2 RL = 150 FREQ = 3.58MHz 0 TO 0.7V .20 .18 .16 .14 .12 .10 PHASE .08 .06 .04 GAIN .02 13 14 15 Direct, two input, resistorless summing is easily realized from the general unity gain mode. By grounding VX2 and applying the two inputs to VX1 and VY1, the output is the exact sum of the applied voltages V1 and V3, relative to common; VOUT = V1 + V3. A diagram of this simple, but potent application is shown below in Figure 38. The AD830 summing circuit possesses several virtues not present in the classic op amp based summing circuits. It has high impedance inputs, no resistors, very precise summing, high reverse isolation and noninverting gain. Achieving this function and performance with op amps requires significantly more components. VP DIFFERENTIAL GAIN - % .08 .07 .06 .05 .04 .03 .02 .01 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE - Volts 1 V1 AD830 GM 8 OUT Figure 40. Differential Gain and Phase for the Circuit of Figure 39 0.2 0.1 VS = 15V 2 A=1 7 3 V3 C AMPLITUDE RESPONSE - dB GM 6 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 10k 100k 1M FREQUENCY - Hz 10M VS = 5V VS = 10V RL = 150 GAIN = +2 4 5 VN VOUT = V1 + V3 Figure 38. Resistorless Summing Amplifier 2 Gain Bandwidth Line Driver A gain of two, without the use of resistors, is possible with the AD830. This is accomplished by grounding VX2, tying the two 100M Figure 41. 0.1 dB Gain Flatness for the Circuit of Figure 39 -14- REV. A DIFFERENTIAL PHASE - Degrees AD830 AC COUPLED LINE RECEIVER The AD830 is configurable as an ac coupled differential amplifier on a single or bipolar supply voltages. All that is needed is inclusion of a few noncritical passive components as illustrated below in Figure 42. A simple resistive network at the X GM input establishes a common-mode bias. Here, the common mode is centered at 6 volts, but in principle can be any voltage within the common-mode limits of the AD830. The 10 k resistors to each input bias the X GM stage with sufficiently high impedance to keep the input coupling corner frequency low, but not too large so that residual bias current induced offset voltage becomes troublesome. For dual supply operation, the 10 k resistors may go directly to ground. The output common is conveniently set by a Zener diode for a low impedance reference to preserve the high frequency CMR. However, a simple resistive divider will work fine and good high frequency CMR can be maintained by placing a compensating resistor in series with the +Y input. The excellent CMRR response of the circuit is shown in Figure 43. A plot of the 0.1 dB flatness from 10 Hz is also shown. With the use of 10 F capacitors, the CMR is >90 dB down to a few tens of hertz. This level of performance is almost impossible to achieve with discrete solutions. +12V INPUT SIGNAL 10F 1 RT AD830 GM 0.1F 8 VOUT 75 75 COAX CABLE ZCM 10F 10k +VS 10k 10k 2k* 2 A=1 7 1000F 3 GM 6 C 75 4 5 +12V 4.7k 10k *OPTIONAL TUNING FOR IMPROVING VERY LOW FREQUENCY CMR. 1N4736 6.8V Figure 42. AC Coupled Line Receiver 120 1 0 COMMON-MODE REJECTION - dB WITH CIRCUIT TRIMMED USING EXTERNAL 2k POTENTIOMETER AMPLITUDE RESPONSE - dB 100 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 80 WITHOUT EXTERNAL 2k POTENTIOMETER 60 40 20 10 100 1k 10k 100k 1M 10M 100M FREQUENCY - Hz -0.9 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M Figure 43. Common-Mode Rejection vs. Frequency for Line Receiver Figure 44. Amplitude Response vs. Frequency for Line Receiver REV. A -15- AD830 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Cerdip (Q) Package 0.005 (0.13) MIN 0.055 (1.4) MAX 8 PIN 1 1 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 5 0.310 (7.87) 0.220 (5.59) 4 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.015 (0.38) 0.008 (0.20) 15 0.023 (0.58) 0.014 (0.36) 0.100 0.070 (1.78) (2.54) 0.030 (0.76) BSC 0 SEATING PLANE Plastic Mini-DIP (N) Package 8 PIN 1 1 4 5 0.280 (7.11) 0.240 (6.10) 0.430 (10.92) 0.348 (8.84) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN SEATING PLANE 0.015 (0.381) 0.008 (0.204) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 8-Pin SOIC (R) Package 0.198 (5.00) 0.188 (4.75) 8 5 0.158 (4.00) 0.150 (3.80) 0.244 (6.200) 0.228 (5.80) 1 4 0.205 (5.20) 0.181 (4.60) 0.102 (2.59) 0.010 (0.25) 0.004 (0.10) 0.094 (2.39) 0.015 (0.38) 0.007 (0.18) 0.045 (1.15) 0.020 (0.50) All brand or product names mentioned are trademarks or registered trademarks of their respective holders. -16- REV. A PRINTED IN U.S.A. 0.050 (1.27) TYP 0.018 (0.46) 0.014 (0.36) C1735-24-10/92 |
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